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for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maximintegrated.com. max15002 dual-output buck controller with tracking/sequencing general description the max15002 is a dual-output, pulse-width-modulated (pwm), step-down dc-dc controller with tracking and sequencing options. the device operates over the input voltage range of 5.5v to 23v or 5v 10%. each pwm controller provides an adjustable output down to 0.6v and delivers at least 15a of load current with excellent load and line regulation. the max15002 is optimized for high- performance, small-size power management solutions. the options of coincident tracking, ratiometric tracking, and output sequencing allow the tailoring of the power-up/power-down sequence depending on the system requirements. each of the max15002 pwm sec- tions utilizes a voltage-mode control scheme with exter- nal compensation, allowing for good noise immunity and maximum flexibility with a wide selection of induc- tor values and capacitor types. each pwm section operates at the same, fixed switching frequency that is programmable from 200khz to 2.2mhz and can be syn- chronized to an external clock signal using the sync input. each converter operating at up to 2.2mhz with 180 out-of-phase, increases the input capacitor ripple frequency up to 4.4mhz, thereby significantly reducing the rms input ripple current and the size of the input bypass capacitor requirement. the max15002 includes internal undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down of the converter. the power- on reset ( reset ) with an adjustable timeout period moni- tors both outputs and provides a reset signal to the processor when both outputs are within regulation. protection features include lossless valley-mode current limit and hiccup mode output short-circuit protection. the max15002 is available in a space-saving, 6mm x 6mm, 40-pin tqfn-ep package and is specified for operation over the -40c to +125c automotive temper- ature range. see the max15003 data sheet for a triple version of the max15002. applications pci express ? host bus adapter power supplies networking/server power supplies point-of-load dc-dc converters features 5.5v to 23v or 5v ?0% input voltage range dual-output synchronous buck controller selectable in-phase or 180 out-of-phase operation output voltages adjustable from 0.6v to 0.85v in lossless valley-mode current sensing or accurate valley current sensing using r sense external compensation for maximum flexibility digital soft-start and soft-stop sequencing or coincident/ratiometric v out tracking individual pgood outputs reset output with a programmable timeout period 200khz to 2.2mhz programmable switching frequency external frequency synchronization hiccup mode short-circuit protection space-saving (6mm x 6mm) 40-pin tqfn package ordering information 19-3099; rev 2; 10/12 pci express is a registered service mark of pci-sig corp. pin configuration appears at end of data sheet. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. part temp range pin-package max15002atl+ -40c to +125c 40 tqfn-ep*
max15002 dual-output buck controller with tracking/sequencing 2 maxim integrated absolute maximum ratings electrical characteristics (v in = 5.5v to 23v or v in = v reg = 4.5v to 5.5v, v dreg_ = v reg , v pgnd_ = v sync = v phase = v sel = 0v, c reg = 2.2f, r rt = 100k ? , c ct = 0.1f, r ilim_ = 60k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at v in = 12v, t a = t j = +25c.) (note 2) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, lx_, csn_ to sgnd..........................................-0.3v to +30v bst_ to sgnd ........................................................-0.3v to +30v bst_ to lx_ ..............................................................-0.3v to +6v reg, dreg_, sync, en_, rt, ct, reset , phase, sel to sgnd ...............................-0.3v to +6v ilim_, pgood_, fb_, comp_, csp_ to sgnd .......-0.3v to +6v dl_ to pgnd_.......................................-0.3v to (v dreg_ + 0.3v) dh_ to lx_ ...............................................-0.3v to (v bst_ + 0.3v) pgnd_ to sgnd, pgnd_ to any other pgnd_.......-0.3v to +0.3v continuous power dissipation (t a = +70c) 40-pin tqfn (derate 37mw/c above +70c) .............2963mw* operating junction temperature range ...........-40 o c to +125c maximum junction temperature .....................................+150c storage temperature range .............................-60c to +150c lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units system specifications 5.5 23.0 v input-voltage range v in v in = v reg = v dreg_ (note 3) 4.5 5.5 v input undervoltage lockout threshold v uvlo v in rising 3.95 4.05 4.15 v input undervoltage lockout hysteresis 0.35 v operating supply current v in = 12v, v fb_ = 0.8v 4.3 6.0 ma shutdown supply current v i n = 12v , v e n _ = 0v , p go od _ unconnected 150 300 a reg voltage regulator output-voltage setpoint v reg v in = 5.5v to 23v 4.9 5.2 v load regulation i reg = 0 to 120ma, v in = 12v 0.2 v digital soft-start/soft-stop soft-start/soft-stop duration 2048 clocks reference voltage steps 64 steps error transconductance amplifier fb_, track_ input bias current -250 +250 na t a = t j = 0c to +85c 0.593 0.600 0.605 v fb_ voltage setpoint v fb t a = t j = -40c to +125c 0.590 0.600 0.608 v fb_ to comp_ transconductance 2.1 ms comp_ output swing 0.75 3.50 v note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . package thermal characteristics (note 1) 40 tqfn-ep junction-to-ambient thermal resistance ( ja )...............27c/w junction-to-case thermal resistance ( jc )......................1c/w * as per jedec51 standard (multilayer board).
max15002 dual-output buck controller with tracking/sequencing 3 maxim integrated parameter symbol conditions min typ max units open-loop gain 80 db unity-gain bandwidth 10 mhz drivers dl_, dh_ break-before-make time c load = 5nf 20 ns low, sinking 100ma 0.9 dh1 on-resistance high, sourcing 100ma 1.3 ? low, sinking 100ma 0.9 dh2 on-resistance high, sourcing 100ma 1.3 ? low, sinking 100ma 0.9 dl1 on-resistance high, sourcing 100ma 1.3 ? low, sinking 100ma 0.9 dl2 on-resistance high, sourcing 100ma 1.3 ? lx_ to pgnd_ on-resistance sinking 10ma 8 ? current-limit and hiccup mode cycle-by-cycle valley current- limit adjustment range v cl v cl_ = v ilim_ /10 50 300 mv v ilim_ = 0.5v 44 54 cycle-by-cycle valley current- limit threshold tolerance v ilim_ = 3v 288 312 mv ilim_ reference current v ilim_ = 0 to 3v, t a = t j = +25c 20 a ilim_ reference current temperature coefficient 3333 ppm/c csp_, csn_ input bias current v csp_ = 0v, v csn_ = -0.3v -20 +20 a number of cumulative current- limit events to hiccup n cl 8 number of consecutive non- current-limit cycles to clear n cl n clr 3 hiccup timeout 4096 clock periods enable/phase/sel en1 threshold v en-th en1 rising 1.19 1.215 1.24 v en1 threshold hysteresis 0.12 v en1 input bias current -1 +1 a phase input high 2v phase input low 0.8 v phase input bias current -1 +1 a sel threshold 20 %v reg sel input bias current -1 +1 a electrical characteristics (continued) (v in = 5.5v to 23v or v in = v reg = 4.5v to 5.5v, v dreg_ = v reg , v pgnd_ = v sync = v phase = v sel = 0v, c reg = 2.2f, r rt = 100k ? , c ct = 0.1f, r ilim_ = 60k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at v in = 12v, t a = t j = +25c.) (note 2)
max15002 dual-output buck controller with tracking/sequencing 4 maxim integrated electrical characteristics (continued) (v in = 5.5v to 23v or v in = v reg = 4.5v to 5.5v, v dreg_ = v reg , v pgnd_ = v sync = v phase = v sel = 0v, c reg = 2.2f, r rt = 100k ? , c ct = 0.1f, r ilim_ = 60k ? , t a = t j = -40c to +125c, unless otherwise noted. typical values are at v in = 12v, t a = t j = +25c.) (note 2) parameter symbol conditions min typ max units pgood_, reset outputs fb_ for pgood_ threshold fb_ falling 0.54 0.555 0.57 v reset , pgood_ output low level sinking 3ma 0.1 v reset , pgood_ leakage -1 +1 a ct charging current 1.8 2 2.2 a ct output low sinking 3ma 0.1 v ct rising 1.8 2.6 ct threshold for reset delay ct falling 1.2 v oscillator switching frequency range (each converter) f sw v sync = 0v, f sw = 1.5 x 10 11 /r rt + 2k 200 2200 khz f sw 1500khz -5 +5 switching frequency accuracy (each converter) f sw > 1500khz -7 +7 % v phase = 0v (dh1 rising to dh2 rising) 180 d eg r ees phase delay v phase = v reg (dh1 rising to dh2 rising) 0 d eg r ees rt voltage v rt 40k ? < r rt < 500k ? 2v minimum controllable on-time t on ( min ) 75 ns minimum off-time t off ( min ) 150 ns sync high-level voltage 2v sync low-level voltage 0.8 v sync internal pulldown resistor 50 100 200 k ? sync frequency range (note 4) 0.4 4.6 mhz sync minimum on-time 30 ns sync minimum off-time 30 ns pwm ramp amplitude (peak-peak) 2v pwm ramp valley 1v note 2: 100% production tested at t a = t j = +25c and t a = t j = +125c. limits at other temperatures are guaranteed by design. note 3: for 5v applications, connect reg directly to in. note 4: the switching frequency is 1/2 of the sync frequency.
converter 1 efficiency vs. load current max15002 toc01 load current (a) efficiency (%) 10 1 50 60 70 80 90 100 40 0.1 100 v in = 6v v in = 12v v in = 16v v out1 = 3.3v f sw = 300khz converter 2 efficiency vs. load current max15002 toc02 load current (a) efficiency (%) 10 1 10 20 30 40 50 60 70 80 90 100 0 0.1 100 v in = 6v v in = 12v v in = 16v v out2 = 1.8v f sw = 300khz converter 1 load regulation max15002 toc03 load current (a) output-voltage accuracy (%) 10 5 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 015 v out1 = 3.3v converter 2 load regulation max15002 toc04 load current (a) output-voltage accuracy (%) 10 5 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 -1.00 015 v out2 = 1.8v internal voltage regulation (reg) max15002 toc05 temperature ( c) v reg (v) 80 60 40 20 4.91 4.92 4.93 4.94 4.95 4.96 4.97 4.98 4.99 5.00 4.90 0 100 v in = 12v c reg = 2.2 f converter-switching frequency vs. r rt max15002 toc06 r rt (k ? ) switching frequency (khz) 600 400 200 100 1000 10,000 10 0800 typical operating characteristics (v in = 12v, referenced to figure 8, t a = t j = +25c, unless otherwise noted.) max15002 dual-output buck controller with tracking/sequencing 5 maxim integrated switching frequency accuracy vs. temperature max15002 toc07 temperature ( c) switching frequency accuracy (%) 125 100 50 75 0 25 -25 -8 -6 -4 -2 0 2 4 6 8 10 -10 -50 150 f sw = 300khz valley current-limit threshold vs. v ilim_ max15002 toc08 v ilim_ (mv) valley current-limit threshold (mv) 3000 2500 2000 1500 1000 100 150 200 250 300 350 50 500 3500
max15002 dual-output buck controller with tracking/sequencing 6 maxim integrated typical operating characteristics (continued) (v in = 12v, referenced to figure 8, t a = t j = +25c, unless otherwise noted.) valley current-limit threshold vs. temperature max15002 toc09 temperature ( c) valley current-limit threshold (mv) 125 100 -25 0 25 50 75 30 40 50 60 70 80 90 100 20 -50 150 r ilim_ = 25.5k ? temp coefficient (nom.) = 3,333ppm/ c switching current vs. frequency max15002 toc10 frequency (khz) switching current (ma) 1700 1200 700 6 7 8 9 10 11 12 13 14 15 5 200 2200 v in = 12v dl_, dh_ unconnected v fb_ = 0v ratiometric startup max15002 toc11 2ms/div 10v/div 0v v in v out1, 2 1v/div 1v/div 0v v en2 = 0v, sel = reg ratiometric shutdown max15002 toc12 1ms/div 500mv/div 500mv/div v out2 v out1 0v v en2 = 0v, sel = reg channel 2 short circuit (ratiometric mode) max15002 toc13 1ms/div 10v/div 1v/div v out2 v out1 v in 0v 0v 2v/div 0v v en2 = 0v, sel = reg channel 1 short circuit (ratiometric mode) max15002 toc14 1ms/div 10v/div 2v/div v out1 v out2 v in 0v 0v 1v/div 0v v en2 = 0v, sel = reg coincident startup max15002 toc15 2ms/div 10v/div v out1, 2 v in 1v/div 0v 1v/div 0v circuit of figure 8, sel = reg coincident shutdown max15002 toc16 2ms/div 500mv/div 500mv/div v out2 v out1 0v
max15002 dual-output buck controller with tracking/sequencing 7 maxim integrated channel 2 short circuit (coincident mode) max15002 toc17 1ms/div 10v/div 0v 0v v out2 v in v out1 1v/div 2v/div 0v channel 1 short circuit (coincident mode) max15002 toc18 1ms/div 10v/div 0v 0v v out1 v in v out2 2v/div 1v/div 0v sequencing startup max15002 toc19 4ms/div 10v/div 0v v in v out1, 2 1v/div 1v/div 0v sel = reg sequencing shutdown max15002 toc20 1ms/div 500mv/div v out1 v out2 500mv/div 0v sel = reg converter 2 output short circuit (sequencing mode) max15002 toc21 1ms/div 10v/div 1v/div v in v out1 v out2 0v 2v/div 0v 0v sel = gnd en/track2 = pgood1 channel 1 output short circuit (sequencing mode) max15002 toc22 1ms/div 10v/div 2v/div v in v out2 v out1 0v 1v/div 0v 0v sel = gnd en/track2 = pgood1 typical operating characteristics (continued) (v in = 12v, referenced to figure 8, t a = t j = +25c, unless otherwise noted.) reset at startup (sequencing mode) max15002 toc23 20ms/div 5v/div 1v/div v out1, 2 v reset 1v/div 0v 0v sel = gnd en/track2 = pgood1 reset at shutdown (sequencing mode) max15002 toc24 1ms/div 5v/div 1v/div v out2 v out1 v reset 1v/div 0v 0v sel = gnd en/track2 = pgood1
max15002 dual-output buck controller with tracking/sequencing 8 maxim integrated typical operating characteristics (continued) (v in = 12v, referenced to figure 8, t a = t j = +25c, unless otherwise noted.) in-phase operation max15002 toc27 1 s/div 5v/div v sync v lx1 v lx2 10v/div 10v/div 0v 0v 0v break-before-make timing max15002 toc28 20ns/div 5v/div v lx1 v dl1 0v 2v/div 0v converter 1 short-circuit condition (hiccup mode) max15002 toc25 4ms/div 500mv/div v out1 i out1 v lx1 v dl1 v pgood1 10v/div 10a/div 5v/div 1v/div 180 out-of-phase operation max15002 toc26 1 s/div 5v/div v sync v lx1 v lx2 10v/div 0v 0v 10v/div 0v load-transient response (i out2 = 100ma to 10a) max15002 toc29 200 s/div 100mv/div ac-coupled v out2 i out2 5a/div 0 load-transient response (i out2 = 5a to 10a) max15002 toc30 200 s/div 100mv/div ac-coupled v out2 i out2 5a/div 0
max15002 dual-output buck controller with tracking/sequencing 9 maxim integrated pin description pin name function 1 reg 5v regulator output. bypass with a 2.2f ceramic capacitor to sgnd. 2 sel track/sequence select input. at startup, connect sel to reg to configure as a dual tracker or connect sel to sgnd to configure as a dual sequencer. note: when configured as a dual sequencer, each rail is independently controlled by en_. 3 pgnd1 controller 1 power-ground connection. connect the input filter capacitors negative terminal, the source of the synchronous mosfet, and the output filter capacitors return to pgnd1. connect externally to sgnd at a single point near the input capacitor return terminal. 4 dl1 controller 1 low-side gate driver output. dl1 is the gate driver output for the synchronous mosfet. 5 dreg1 controller 1 low-side gate driver supply. connect externally to reg and the anode of the boost diode. connect a minimum of 0.1f ceramic capacitor from dreg1 to pgnd1. 6 lx1 controller 1 high-side mosfet source connection/synchronous mosfet drain connection. connect the inductor and the negative side of the boost capacitor to lx1. 7 dh1 controller 1 high-side gate driver output. dh1 drives the gate of the high-side mosfet. 8 bst1 controller 1 high-side gate driver supply. connect bst1 to the cathode of the boost diode and to the positive terminal of the boost capacitor. 9 csn1 controller 1 negative current-sense input. connect csn1 to the synchronous mosfet drain (connected to lx1). when using a current-sense resistor, connect csn1 to the junction of a low-side mosfets source and the current-sense resistor. see figure 10. 10 csp1 controller 1 positive current-sense input. connect csp1 to the synchronous mosfet source (connected to pgnd1). when using a current-sense resistor, connect csp1 to the pgnd1 end of the current-sense resistor. 11 ilim1 controller 1 valley current-limit set output. connect a 25k ? to 150k ? resistor, r ilim1 , from ilim1 to sgnd to program the valley current-limit threshold from 50mv to 300mv. ilim1 sources 20a out to r ilim1 . the resulting voltage divided by 10 is the valley current-limit threshold. when using a precision current-sense resistor, connect a resistive divider from reg to ilim1 to sgnd to set the valley current limit. see figure 10. 12 comp1 controller 1 error transconductance amplifier output. connect comp1 to the compensation feedback network. 13 en1 controller 1 enable input. en1 must be above 1.24v, v en-th , for the pwm controller to start output 1. controller 1 is the master. use the master as the highest output voltage in a coincident tracking configuration. 14 fb1 controller 1 feedback regulation point. connect to the center tap of a resistive divider from the converter output to sgnd to set the output voltage. the fb1 voltage regulates to v fb (0.6v). 15 pgood1 controller 1 power-good output. open-drain pgood1 output goes high impedance (releases) when fb1 is above 0.925 x v fb (0.555v). 16 pgnd2 controller 2 power ground connection. connect the input filter capacitors negative terminal, the source of the synchronous mosfet, and the output filter capacitors return to pgnd2. connect externally to sgnd at a single point near the input capacitor return terminal. 17 dl2 controller 2 low-side gate driver output. dl2 is the gate driver output for the synchronous mosfet. 18 dreg2 controller 2 low-side gate driver supply. connect externally to reg and the anode of the boost diode. connect a minimum of a 0.1f ceramic capacitor from dreg2 to pgnd2. 19 lx2 controller 2 high-side mosfet source connection/synchronous mosfet drain connection. connect the inductor and the negative side of the boost capacitor to lx2.
max15002 dual-output buck controller with tracking/sequencing 10 maxim integrated pin description (continued) pin name function 20 dh2 controller 2 high-side gate driver output. dh2 drives the gate of the high-side mosfet. 21 bst2 controller 2 high-side gate driver supply. connect bst2 to the cathode of the boost diode and to the positive terminal of the boost capacitor. 22 csn2 controller 2 negative current-sense input. connect csn2 to the synchronous mosfet drain (connected to lx2). when using a current-sense resistor, connect csn2 to the junction of the low-side mosfets source and the current-sense resistor. see figure 10. 23 csp2 controller 2 positive current-sense input. connect csp2 to the synchronous mosfet source (connected to pgnd2). when using a current-sense resistor, connect csp2 to the pgnd2 end of the current-sense resistor. 24 ilim2 controller 2 valley current-limit set output. connect a 25k ? to 150k ? resistor, r ilim2 , from ilim2 to sgnd to program the valley current-limit threshold from 50mv to 300mv. ilim2 sources 20a out to r ilim2 . the resulting voltage divided by 10 is the valley current-limit threshold. when using a precision current-sense resistor, connect a resistive divider from reg to ilim2 to sgnd to set the valley current limit. see figure 10. 25 comp2 controller 2 error transconductance amplifier output. connect comp2 to the compensation feedback network. 26 en/track2 controller 2 enable/tracking input. see figure 2. when sequencing, en/track2 must be above 1.24v for the pwm controller 2 to start. coincident trackingconnect the same resistive divider used for fb2, from output 1 to en/track2 to sgnd. ratiometric trackingconnect en/track2 to analog ground. 27 fb2 controller 2 feedback regulation point. connect to the center tap of a resistive divider from the converter output to sgnd to set the output voltage. the fb2 voltage regulates to v fb (0.6v). 28 pgood2 controller 2 power-good output. open-drain pgood2 output goes high impedance (releases) when fb2 is above 0.925 x v fb (0.555v). 29C33 n.c. no connection. not internally connected. 34 sync synchronization input. drive with a frequency at least 20% higher than two times the frequency programmed using the rt pin. the switching frequency is 1/2 the sync frequency. connect sync to sgnd when not used. 35 sgnd analog ground connection. connect sgnd and pgnd_ together at one point near the input bypass capacitor return terminal. 36 rt oscillator timing resistor connection. connect a 750k ? to 68k ? resistor from rt to sgnd to program the switching frequency from 200khz to 2.2mhz. 37 phase phase select input. connect phase to sgnd for 180 out-of-phase operation between the controllers. connect to reg for in phase operation. 38 reset reset output. open-drain reset output releases after all pgoods are released and timeout programmed by ct finishes. 39 ct reset timeout capacitor connection. connect a timing capacitor from ct to analog ground to set the reset delay. ct sources 2a into the timing capacitor. when the voltage at ct passes 2v, open-drain reset goes high impedance. 40 in supply input connection. connect to an external voltage source from 5.5v to 23v. for 4.5v to 5.5v input application, connect in and reg together. ep exposed pad. solder the exposed pad to a large sgnd plane.
max15002 dual-output buck controller with tracking/sequencing 11 maxim integrated functional diagrams reg v ref vr1 down1 clk1 fb1 comp1 ldo 1.24v 1.12v shdn res overload management vregok in sel pwm controller 1 en1 ct reset 1.24v on 1.12v off seq_ en en osc ovl config csp1 sgnd csn1 ilim1 bst1 dh1 lx1 dreg1 dl1 pgnd1 ovl_ r q set dominant s 0.925 x v ref fb1 pgpd1 pgpd_ digital soft-start and stop 0.6v ref config selector e/a cpwm clk1 level shift reset timeout ramp clk2 current- limit set sync rt phase en1 ovl1 imax1 clk1 seq_ pgood1 max15002
max15002 dual-output buck controller with tracking/sequencing 12 maxim integrated detailed description the max15002 is a dual-output, pulse-width-modulat- ed (pwm), step-down, dc-dc controller with tracking and sequencing options. the device operates over the input voltage range of 5.5v to 23v or 5v 10%. each pwm controller provides an adjustable output down to 0.6v and delivers at least 15a of load current with excellent load and line regulation. each of the max15002 pwm sections utilizes a volt- age-mode control scheme for good noise immunity and offers external compensation allowing for maximum flexibility with a wide selection of inductor values and capacitor types. the device operates at a fixed switch- ing frequency that is programmable from 200khz to 2.2mhz and can be synchronized to an external clock signal using the sync input. each converter, operating at up to 2.2mhz with 180 out-of-phase, increases the input capacitor ripple frequency up to 4.4mhz, reduc- ing the rms input ripple current and the size of the input bypass capacitor requirement significantly. the max15002 provides coincident tracking, ratiometric tracking, and sequencing. this allows tai- loring of the power-up/power-down sequence depend- ing on the system requirements. the max15002 features lossless valley-mode current- limit protection by monitoring the voltage drop across the synchronous mosfets on-resistance to sense the inductor current. the max15002s internal current source exhibits a positive temperature coefficient to help compensate for the mosfets temperature coefficient. use an external voltage-divider when a more precise current limit is desired. this divider along with a preci- sion shunt resistor allows for more accurate current limit. the max15002 includes internal undervoltage lockout with hysteresis, digital soft-start/soft-stop for glitch-free power-up and power-down of the converter. the power-on reset ( reset ) with adjustable timeout period monitors both outputs and provides a reset signal to the processor indicating when the outputs are within regulation. protection features include lossless valley- mode current limit and hiccup mode output short-cir- cuit protection. functional diagrams (continued) v ref v ref vr2 down2 en/ track2 fb2 comp2 en2 res overload management pwm controller 2 en/track2 1.24v on 1.12v off ovl config csp2 csn2 ilim2 bst2 dh2 lx2 dreg2 dl2 pgnd2 ovl_ en config r q set dominant s 0.925 x v ref fb2 pgpd2 digital soft-start and stop e/a cpwm clk2 level shift ramp current- limit set clk2 shdn en1 ovl2 imax2 clk2 seq_ seq_ pgood2 max15002 sel_ clk2
max15002 dual-output buck controller with tracking/sequencing 13 maxim integrated internal undervoltage lockout (uvlo) v in must exceed the default uvlo threshold before any operation can commence. the uvlo circuitry keeps the mosfet drivers, oscillator, and all the internal circuitry shut down to reduce current consumption. the uvlo rising threshold is 4.05v with 350mv hysteresis. digital soft-start/soft-stop the max15002 soft-start feature allows the load voltage to ramp up in a controlled manner, eliminating output- voltage overshoot. soft-start begins after v in exceeds the undervoltage lockout threshold and the enable input is above 1.24v. the soft-start circuitry gradually ramps up the reference voltage. this controls the rate of rise of the output voltage and reduces input surge currents during startup. the soft-start duration is 2048 clock cycles. the output voltage is incremented through 64 equal steps. the output reaches regulation when soft-start is completed, regardless of output capacitance and load. soft-stop commences when the enable input falls below 1.12v. the soft-stop circuitry ramps down the reference voltage controlling the output voltage rate of fall. the output voltage is decremented through 64 equal steps in 2048 clock cycles. internal linear regulator (reg) reg is the output terminal of a 5v ldo powered from in which provides power to the ic. connect reg externally to dreg_ to provide power for the low-side mosfet gate driver. bypass reg to sgnd with a minimum 2.2f ceramic capacitor. place the capacitor physically close to the max15002 to provide good bypassing. reg is intended for powering only the internal circuitry and should not be used to supply power to external loads. reg can source up to 120ma. this current, i reg , includes quiescent current (i q ) and gate drive current (i dreg_ ): i reg = i q + [f sw x (q ghs_ + q gls_ )] where q ghs_ + q gls_ is the total gate charge of each of the respective high- and low-side external mosfets at v gate = 5v. f sw is the switching frequency of the converter and i q is the quiescent current of the device at the switching frequency. mosfet gate drivers dreg_ is the supply input for the low-side mosfet dri- ver. connect dreg_ to reg externally. everytime the low-side mosfet switches on, high peak current is drawn from dreg_ for a short amount of time. adding an rc filter (1 ? to 3.3 ? and 2.2f//0.1f ceramic capacitors are typical) from reg to dreg_ filters out high-peak currents. bst_ supplies the power for the high-side mosfet dri- vers. connect the bootstrap diode from bst_ to dreg_ (anode at dreg_ and cathode at bst_). connect a bootstrap 0.1f or higher ceramic capacitor between bst_ and lx_. though not always necessary, it may be useful to insert a small resistor (4.7 ? to 22 ? ) in series with the bst_ pin and the cathode of the bootstrap diode for additional noise immunity. the high-side (dh_) and low-side (dl_) drivers drive the gates of the external n-channel mosfets. the dri- vers 2a peak source- and sink-current capability pro- vides ample drive for the fast rise and fall times of the switching mosfets. faster rise and fall times result in reduced switching losses. the gate driver circuitry also provides a break-before- make time (20ns typ) to prevent shoot-through currents during transition. oscillator/synchronization input/phase staggering (rt, sync, phase) use an external resistor at rt to program the max15002 switching frequency from 200khz to 2.2mhz. choose the appropriate resistor at rt to cal- culate the desired output switching frequency (f sw ): f sw (hz) = 1.5 x 10 11 /(r rt + 2000) ? connect an external clock at sync for external clock synchronization. a rising clock edge on sync is inter- preted as a synchronization input. if the sync signal is lost, the internal oscillator takes control of the switching rate, returning the switching frequency to that set by r rt . this maintains output regulation even with intermit- tent sync signals. for proper synchronization, the external frequency must be at least 20% higher than twice the frequency programmed through the rt input. the switching frequency is 1/2 the sync frequency. connect sync to sgnd when not used. connect phase to sgnd for 180 out-of-phase opera- tion between the controllers. connect phase to reg for in-phase operation.
max15002 dual-output buck controller with tracking/sequencing 14 maxim integrated coincident/ratiometric tracking (sel, en/track2) the enable/tracking input in conjunction with digital soft-start and soft-stop provides coincident/ratiometric tracking. see figure 1. track an output voltage by con- necting a resistive divider from the output being tracked to the enable/tracking input. for example, for v out2 to coincidentally track v out1 , connect the same resistive divider used for fb2, from out1 to en/track2 to sgnd. see figure 2 and the coincident startup and coincident shutdown graphs in the typical operating characteristics . track ratiometrically by connecting en/track2 to sgnd. this synchonizes the soft-start and soft-stop of all the controllers references, and hence their respective output voltages will track ratiometrically. see figure 2 and the ratiometric startup and ratiometric shutdown graphs in the typical operating characteristics . connect sel to reg to configure as a dual tracker. when the max15002 converter is configured as a tracker, the output short-circuit fault situations at master or slave output is handled carefully so that either the master or slave output does not stay on when the other output is shorted to the ground. when the slave is shorted and enters in hiccup mode, the master will soft- stop. when the master is shorted and the part enters in hiccup mode, the slave will ratiometrically soft-stop. coming out of the hiccup, all outputs will soft-start coin- cidently or ratiometrically depending on their initial con- figuration. see the typical operating characteristics for the output behavior during the fault conditions. during the thermal shutdown or power-off, when the input falls below its uvlo, the output voltages fall down at the rate depending on the respective output capacitor and load. see figure 1. output-voltage sequencing (sel, en/track2, pgood) referring to figure 1c, when sequencing, the enable/tracking input must be above 1.24v for each pwm controller to start. the pgood_ outputs and en/track2 inputs can be daisy-chained to generate power sequenc- ing. open-drain pgood_ outputs go high impedance when fb_ is above the pgood_ threshold (555mv typ). connect the power-good output to the enable/tracking input to set when the other controller will start. see figure 2. connect sel to sgnd to configure as a dual sequencer. v out1 v out2 v out1 v out2 v out1 v out2 soft-start soft-stop soft-start soft-stop a) coincident tracking outputs b) ratiometric tracking outputs soft- start soft-stop c) sequenced outputs figure 1. graphical representation of coincident tracking, ratiometric tracking, and pgood sequencing
max15002 dual-output buck controller with tracking/sequencing 15 maxim integrated error amplifier the output of the internal error transconductance amplifier (comp_) is provided for frequency compen- sation (see the compensation design guidelines sec- tion). the inverting input is fb_ and the output comp_. the error transamplifier has an 80db open-loop gain and a 10mhz gbw product. output short-circuit protection (hiccup mode) the current-limit circuit employs a valley current-limiting algorithm that either uses a shunt or the synchronous mosfets on-resistance as the current-sensing ele- ment. once the high-side mosfet turns off, the volt- age across the current-sensing element is monitored. if this voltage does not exceed the current-limit threshold, the high-side mosfet turns on normally at the start of the next cycle. if the voltage exceeds the current-limit threshold just before the beginning of a new pwm cycle, the controller skips that cycle. during severe overload or short-circuit conditions, the switching fre- quency of the device appears to decrease because the on-time of the low-side mosfet extends beyond a clock cycle. if the current-limit threshold is exceeded for more than eight cumulative clock cycles (n cl ), the device shuts down (both dh and dl are pulled low) for 4096 clock cycles (hiccup timeout) and then restarts with a soft- start sequence. if three consecutive cycles pass with- out a current-limit event, the count of n cl is cleared (see figure 3). hiccup mode protects against a contin- uous output short circuit. coincident tracking pgood sequencing en/track2 sel reg v in en1 ratiometric tracking r a r b r a r b v in en1 p good1 en/track2 reg v in en1 v out2 fb2 v out1 en/track2 sel sel reg figure 2. ratiometric tracking, coincident tracking, pgood sequencing configurations
max15002 dual-output buck controller with tracking/sequencing 16 maxim integrated pwm controller design procedures setting the switching frequency connect a 750k ? to 68k ? resistor from rt to sgnd to program the switching frequency from 200khz to 2.2mhz. calculate the switching frequency using the following equation: f sw (hz) = 1.5 x 10 11 /(r rt + 2000) ? higher frequencies allow designs with lower inductor values and less output capacitance. consequently, peak currents and i 2 r losses are lower at higher switching frequencies, but core losses, gate-charge currents, and switching losses increase. effective input voltage range although the max15002 converters can operate from input supplies ranging from 5.5v to 23v, the input volt- age range can be effectively limited by the max15002 duty-cycle limitations for a given output voltage. the maximum input voltage is limited by the minimum on- time (t on(min) ): where t on(min) is 75ns. the minimum input voltage is limited by the maximum duty cycle and is calculated using the following equa- tion: where t off(min) typically is equal to 150ns. inductor selection three key inductor parameters must be specified for operation with the max15002: inductance value (l), peak inductor current (i peak ), and inductor saturation current (i sat ). the minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-to-peak inductor current ( ? i p-p ). higher ? i p-p allows for a lower inductor value. a lower inductance value minimizes size and cost and improves large-signal and transient response. however, efficiency is reduced due to higher peak cur- rents and higher peak-to-peak output voltage ripple for the same output capacitor. a higher inductance increases efficiency by reducing the ripple current, however resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current lev- els especially when the inductance is increased without also allowing for larger inductor dimensions. a good rule of thumb is to choose ? i p-p equal to 30% of the full load current. calculate the inductance using the follow- ing equation: v in and v out are typical values so that efficiency is optimum for typical conditions. the switching frequen- cy is programmable between 200khz and 2.2mhz (see oscillator/synchronization input/phase staggering (rt, sync, phase) section). the peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. see the output capacitor selection section to verify that the worst-case output current ripple is acceptable. the inductor satu- ration current (i sat ) is also important to avoid runaway current during continuous output short-circuit condi- tions. select an inductor with an i sat specification high- er than the maximum peak current. l out in out in sw p p vvv vf i = ? () ? ? v v tf in min out off min sw () () ? () 1 v v tf in max out on min sw () () current limit count of 8 n cl in clr initiate hiccup timeout n ht count of 3 n clr in clr figure 3. hiccup-mode block diagram
max15002 dual-output buck controller with tracking/sequencing 17 maxim integrated input capacitor selection the discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to withstand the input ripple current and keep the input voltage rip- ple within design requirements. the 180 ripple phase operation increases the frequency of the input capaci- tor ripple current to twice the individual converter switching frequency. when using ripple phasing, the worst-case input capacitor ripple current is when the one converter with the highest output current is on. the input voltage ripple is comprised of ? v q (caused by the capacitor discharge) and ? v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of ? v q and ? v esr that peaks at the end of the on-cycle. calculate the input capacitance and esr required for a specified ripple using the following equations: where: i load(max) is the maximum output current, ? i p-p is the peak-to-peak inductor current, and f sw is the switching frequency. for the condition with only one converter on, calculate the input ripple current using the following equation: the max15002 includes uvlo hysteresis to avoid pos- sible unintentional chattering during turn-on. use addi- tional bulk capacitance if the input source impedance is high. at lower input voltage, additional input capaci- tance helps avoid possible undershoot below the under- voltage lockout threshold during transient loading. output capacitor selection the allowed output voltage ripple and the maximum deviation of the output voltage during load steps deter- mine the required output capacitance and its esr. the output ripple is mainly composed of ? v q (caused by the capacitor discharge) and ? v esr (caused by the voltage drop across the equivalent series resistance of the output capacitor). the equations for calculating the output capacitance and its esr are: ? v esr and ? v q are not directly additive because they are out of phase from each other. if using ceramic capacitors, which generally have low esr, ? v q domi- nates. if using electrolytic capacitors, ? v esr dominates. the allowable deviation of the output voltage during fast load transients also affects the output capacitance, its esr, and its equivalent series inductance (esl). the output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. the response time (t response ) depends on the gain bandwidth of the converter (see the compensation design guidelines section). the resis- tive drop across the output capacitors esr, the drop across the capacitors esl, and the capacitor dis- charge cause a voltage droop during the load-step (i step ). use a combination of low-esr tantalum/alu- minum electrolyte and ceramic capacitors for better load-transient and voltage-ripple performance. nonleaded capacitors and capacitors in parallel help reduce the esl. keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. use the following equations to calculate the required esr, esl, and capacitance value during a load step: where i step is the load step, t step is the rise time of the load step, and t response is the response time of the controller. e esr step out step response q e esl step step v i c it v vt i sr = = sl = ? ? ? c i vf v i out pp qsw e esr pp = sr = ? ? ? ? ? ? 8 2 i vvv v cin rms i load max out in out in () _ = () ? ? i vv v vf l pp in out out in sw ? ? () = e esr load max pp c in load max out in qsw v i i i v v vf sr = = ? ? ? () () + ? ? ? ? ? ? ? ? ? ? ? ? ? 2
max15002 dual-output buck controller with tracking/sequencing 18 maxim integrated setting the current limit connect a 25k ? to 150k ? resistor, r ilim_ , from ilim_ to sgnd to program the valley current-limit threshold (v cl ) from 50mv to 300mv. ilim_ sources 20a out to r ilim_ . the resulting voltage divided by 10 is the valley current-limit threshold. the max15002 uses a valley current-sense method for current limiting. the voltage drop across the low-side mosfet due to its on-resistance is used to sense the inductor current. the voltage drop (v valley ) across the low-side mosfet at the valley point and at i load is: r ds(on) is the on-resistance of the low-side mosfet, i load is the rated load current, and ? i p-p is the peak- to-peak inductor current. the r ds(on) of the mosfet varies with temperature. calculate the r ds(on) of the mosfet at its operating junction temperature at full load using the mosfet datasheet. to compensate for this temperature varia- tion, the 20a ilim reference current has a temperature coefficient of 3333ppm/c. this allows the valley cur- rent-limit threshold (v cl ) to track and partially compen- sate for the increase in the synchronous mosfets r ds(on) with increasing temperature. use the following equation to calculate r ilim : where i cl(max) is the maximum current limit. figure 4 illustrates the effect of the max15002 ilim ref- erence current temperature coefficient to compensate for the variation of the mosfet r ds(on) over the oper- ating junction temperature range. power mosfet selection when choosing the mosfets, consider the total gate charge, r ds(on) , power dissipation, the maximum drain- to-source voltage and package thermal impedance. the product of the mosfet gate charge and on-resistance is a figure of merit, with a lower number signifying better performance. choose mosfets that are optimized for high-frequency switching applications. the average gate- drive current from the max15002s output is proportional to the frequency and gate charge required to drive the mosfet. the power dissipated in the max15002 is pro- portional to the input voltage and the average drive cur- rent (see the power dissipation section). compensation design guidelines the max15002 uses a fixed-frequency, voltage-mode control scheme that regulates the output voltage by dif- ferentially comparing the output voltage against a fixed reference. the subsequent error voltage that appears at the error amplifier output (comp) is compared against an internal ramp voltage to generate the required duty cycle of the pulse-width modulator. a second order low- pass lc filter removes the switching harmonics and passes the dc component of the pulse-width-modulat- ed signal to the output. the lc filter, which has an atten- uation slope of -40db/dec, introduces 180 of phase shift at frequencies above the lc resonant frequency. this phase shift, in addition to the inherent 180 of phase shift of the regulators self-governing (negative) feedback system, poses the potential for positive feed- back. the error amplifier and its associated circuitry are designed to compensate for this instability to achieve a stable closed-loop system. the basic regulator loop consists of a power modulator (comprised of the regulators pulse-width modulator, associated circuitry, and lc filter), an output feedback divider, and an error amplifier. the power modulator has a dc gain set by v in /v ramp , where v ramp s ampli- tude is typically 2v p-p . the output filter is effectively modeled as a double pole and a single zero set by the output inductance (l), the output capacitance (c out ), the dc resistance of the inductor (dcr), and its equiv- alent series resistance (esr). r ilim ri i ds on cl max pp _ () ( ) = ? ? ? ? ? ? ? ? ? 2 10 20 + ? () ? ? ? ? ?? 10 1 3 333 10 25 63 .tc vi i valley r ds on load pp = () ? ? ? ? ? ? ? ? ? 2 valley current-limit threshold and r ds(on) vs. temperature max15002 fig04 temperature ( c) vi lim_ and r ds(on) (normalized) 130 110 70 90 -10 10 30 50 -30 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.5 -50 150 r ds(on) v ilim_ r ilim_ = 25.5k ? figure 4. current-limit trip point and v rds(on) vs. temperature
max15002 dual-output buck controller with tracking/sequencing 19 maxim integrated below are equations that define the power modulator: the switching frequency is programmable between 200khz and 2.2mhz using an external resistor at rt. typically, the crossover frequency (f co ), which is the frequency when the systems closed-loop gain is equal to unity (crosses the 0db axis)should be set at or below one-tenth the switching frequency (f sw /10) for stable, closed-loop response. the max15002 provides an internal transconductance amplifier with its inverting input and its output available to the user for external frequency compensation. the flexibility of external compensation for each converter offers wide selection of output filtering components, especially the output capacitor. for cost-sensitive appli- cations, use aluminum electrolytic capacitors and for space-sensitive applications, use low-esr tantalum or multilayer ceramic chip (mlcc) capacitors at the out- put. the higher switching frequencies of the max15002 allow the use of mlcc as the primary filter capacitor(s). first, select the passive and active power components that meet the applications output ripple, component size, and component cost requirements. second, choose the small-signal compensation components to achieve the desired closed-loop frequency response and phase margin as outlined below. closed-loop response and compensation of voltage-mode regulators the power modulators lc lowpass filter exhibits a vari- ety of responses, depending on the value of the l and c (and their parasitics). one such response is shown in figure 5a. in this exam- ple, the power modulators uncompensated crossover is approximately 1/6 th the desired crossover frequency, f co . note also, the uncompensated roll-off through the 0db plane follows the double-pole, -40db/dec slope and approaches 180 of phase shift, indicative of a potentially unstable system. together with the inherent 180 of phase delay in the negative feedback system, this can lead to near 360 or positive feedbackan unstable system. the desired (compensated) roll-off follows a -20db/dec slope (and commensurate 90 of phase shift), and, in this example, occurs at approximately 6x the uncom- pensated crossover frequency, f co . in this example, a type ii compensator provides for stable closed-loop operation, leveraging the +20db/dec slope of the capacitors esr zero (see figure 5b). g f f mod dc v in v ramp v in v lc lc out r out esr r out dcr lc out esr esr c out () == = = 2 1 2 1 2 1 2 + + ? ? ? ? ? ? power modulator gain and phase response with lossy bulk output capacitors (aluminum electrolytics) max15002 fig05a magnitude (db) phase (degrees) -60 -40 -20 0 20 40 -80 100 1k 10k frequency (hz) 100k 1m 10m 10 -135 -90 -45 0 45 90 -180 |g mod | |g mod | asymptote f lc f esr < g mod figure 5a. power modulator gain and phase response (large, bulk c out ) max15002 fig05b magnitude (db) phase (degrees) frequency (hz) -60 -40 -20 0 20 40 60 80 -80 -135 -90 -45 0 45 90 135 180 -180 power modulator and type ii compensator gain and phase response with lossy bulk output capacitors (aluminum electrolytics) 100 1k 10k 100k 1m 10m 10 < g e/a |g e/a | |g mod | f lc f esr f co < g mod figure 5b. power modulator (large, bulk c out ) and type ii compensator responses
max15002 dual-output buck controller with tracking/sequencing 20 maxim integrated the type ii compensators mid-frequency gain (approximately 4db shown here) is designed to com- pensate for the power modulators attenuation at the desired crossover frequency, f co (g e/a + g mod = 0db at f co ). in this example, the power modulators inherent -20db/dec roll-off above the esr zero (f esr ) is lever- aged to extend the active regulation gain-bandwidth of the voltage regulator. as shown in figure 5b, the net result is a 2x increase in the regulators gain bandwidth while providing greater than 55 of phase margin (the difference between g e/a and g mod respective phases at crossover, f co ). other filter schemes pose their own problems. for instance, when choosing high-quality filter capacitor(s), e.g., mlccs, and inductor, with minimal parasitics, the inherent esr zero can occur at a much higher frequen- cy, as shown in figure 5c. as with the previous example, the actual gain and phase response is overlaid on the power modulators asymptotic gain response. one readily observes the more dramatic gain and phase transition at or near the power modulators resonant frequency, f lc , versus the gentler response of the previous example. this is due to the components lower parasitics (ocr and esr) and corresponding higher frequency of the inherent esr zero frequency. in this example, the desired crossover frequency occurs below the esr zero frequency. in this example, a compensator with an inherent mid- frequency double-zero response is required to mitigate the effects of the filters double-pole. such is available with the type iii topology. as demonstrated in figure 5d, the type iiis mid-fre- quency double-zero gain (exhibiting a +20db/dec slope, noting the compensators pole at the origin) is designed to compensate for the power modulators double-pole -40db/dec attenuation at the desired crossover frequency, f co (again, g e/a + g mod = 0db at f co ). see figure 5d. in the above example, the power modulators inherent (mid-frequency) -40db/decade roll-off is mitigated by the mid-frequency double zeros +20db/dec gain to extend the active regulation gain-bandwidth of the volt- age regulator. as shown in figure 5d, the net result is an approximate doubling in the regulators gain band- width while providing greater than 60 of phase margin (the difference between g e/a and g mod respective phases at crossover, f co ). design procedures for both type ii and type iii com- pensators are shown below. magnitude (db) phase (degrees) frequency (hz) -60 -40 -20 0 20 40 -80 -135 -90 -45 0 45 90 -180 power modulator gain and phase response with low-parasitic output capacitors (mlccs) max15002 fig05c 100 1k 10k 100k 1m 10m 10 |g mod | |g mod | asymptote f lc f esr < g mod figure 5c. power modulator gain and phase response (high- quality c out ) power modulator and type iii compensator gain and phase response with low parasitic output capacitors (mlccs) max15002 fig05d magnitude (db) phase (degrees) frequency (hz) -60 -40 -20 0 20 40 60 80 -80 -203 -135 -68 0 68 135 203 270 -270 100 1k 10k 100k 1m 10m 10 < g e/a |g e/a | |g mod | f lc f esr f co < g mod figure 5d. power modulator (high-quality c out ) and type iii compensator responses
max15002 dual-output buck controller with tracking/sequencing 21 maxim integrated type ii: compensation when f co > f esr when the f co is greater than f esr , a type ii compensa- tion network provides the necessary closed-loop response. the type ii compensation network provides a midband compensating zero and high-frequency pole (see figures 6a and 6b). r f c f provides the midband zero f mid,zero , and r f c cf provides the high-frequency pole f high,pole . use the following procedure to calculate the compen- sation network components. 1) calculate the f zero,esr and lc double pole, f lc : 2) calculate the unity-gain crossover frequency as: 3) determine r f from the following: note: r f is derived by setting the total loop gain at crossover frequency to unity, e.g., g ea (f co ) x g m (f co ) = 1v/v. the transconductance error amplifier gain is g ea (f co ) = g m x r f while the modulator gain is: the total loop gain can be expressed logarithmically as follows: where v ramp is the peak-to-peak ramp amplitude equal to 2v. 4) place a zero at or below the lc double pole, f lc : 5) place a high-frequency pole at or below f p = 0.5 x f sw : 6) choose an appropriately sized r 1 (connected from out_ to fb_, start with a 10k ? ). once r 1 is select- ed, calculate r 2 using the following equation: where v fb = 0.6v. r r v fb v out v fb 21 = ? c cf r f f sw = 1 c f r f f lc = 1 2 2 2 2 0log g r + 0log 10 mf 10 ? ? ? ? ( esr v v fl in fb co ) ) ? ? ? ? ? ? ? ? = vv db out ramp 0 gf mod co v in v ramp esr f co l v fb v out () = 2 r vflv v v g esr f ramp co out out in m = () 2 f co f sw 10 f f esr esr c out lc lc out = = 1 2 1 2 r 1 fb r f comp v out v ref c cf c f r 2 - + g m figure 6a. type ii compensation network gain (db) 1st asymptote g mod v ref v out -1 ( c f ) -1 (rad/sec) 3rd asymptote g mod v ref v out -1 ( c cf ) -1 2nd asymptote g mod v ref v out -1 r f 1st pole (at origin) 2nd pole r f c cf 1st zero r f c f figure 6b. type ii compensation network response
max15002 dual-output buck controller with tracking/sequencing 22 maxim integrated type iii: compensation when f co < f esr as indicated above, the position of the output capaci- tors inherent esr zero is critical in designing an appro- priate compensation network. when low-esr ceramic output capacitors are used, the esr zero frequency (f esr ) is usually much higher than unity crossover fre- quency (f co ). in this case, a type iii compensation net- work is recommended (see figure 7a). as shown in figure 7b, the type iii compensation net- work introduces two zeros and three poles into the con- trol loop. the error amplifier has a low-frequency pole at the origin, two zeros, and two higher frequency poles at the following frequencies: two midband zeros (f z1 and f z2 ) are designed to can- cel the pair of complex poles introduced by the lc filter. f p1 = at the origin (0hz) f p1 introduces a pole at zero frequency (integrator) for nulling dc output-voltage errors. depending on the location of the esr zero (f esr ), f p2 can be used to cancel it, or to provide additional atten- uation of the high-frequency output ripple. f p3 attenuates the high-frequency output ripple. the locations of the zeros and poles should be such that the phase margin peaks around f co . set the ratios of f co -to-f z and f p -to-f co equal to one another, e.g., f co = f p = 5 is a good number to get about f z f co 60 of phase margin at f co . whichever technique, it is important to place the two zeros at or below the double pole to avoid the conditional stability issue. the following procedure is recommended: 1) select a crossover frequency, f co , at or below one- tenth the switching frequency: 2) calculate the lc double-pole frequency, f lc : 3) select r f 10k ? . 4) place compensators first zero at or below the output filters double pole, f lc , as follows: c rf f flc = 1 205 . f lc lc out = 1 2 f co f sw 10 f rcc r cc cc p ffcf f fcf fcf 3 1 2 1 2 = () = + || f rc p ii 2 1 2 = f rc f crr z ff z ii 1 2 1 1 2 1 2 = = + () r 1 r f comp v out v ref r 2 r i c i c f c cf - + g m fb figure 7a. type iii compensation network figure 7b. type iii compensation network response gain (db) 1st asymptote r i c f -1 3rd asymptote r f c i 5th asymptote r i c cf -1 4th asymptote r f r i (rad/sec) 2nd asymptote r f r i -1 1st pole (at origin) 2nd pole r i c i 3rd pole r f c cf 1st zero r f c f 2nd zero r i c i f rc z ff 1 1 2 =
max15002 dual-output buck controller with tracking/sequencing 23 maxim integrated 5) the gain of the modulator (gain mod )comprised of the regulators pulse-width modulator, lc filter, feedback divider, and associated circuitryat crossover frequency is: the gain of the error amplifier (gain e/a ) in midband fre- quencies is: gain e/a = 2 x f co x c i x r f the total loop gain as the product of the modulator gain and the error-amplifier gain at f co should be equal to 1, as follows: 6) for those situations where f lc < f co < f esr < f sw /2as with low-esr tantalum capacitorsthe compensators second pole (f p2 ) should be used to cancel f esr . this provides additional phase margin. viewed mathematically on the system bode plot, the loop gain plot maintains its +20db/dec slope up to 1/2 of the switching frequency verses flattening out soon after the 0db crossover. then set: f p2 = f esr if a ceramic capacitor is used, the capacitor esr zero, f esr , is likely to be located even above one- half of the switching frequency, that is f lc < f co < f sw /2 < f esr . in this case, the frequency of the sec- ond pole (f p2 ) should be placed high enough not to significantly erode the phase margin at the crossover frequency. for example, it can be set at 5 x f co , so that its contribution to phase loss at the crossover frequency f co is only about 11: f p2 = 5 x f co once f p2 is known, calculate r i : 7) place the second zero (f z2 ) at 0.2 x f co or at f lc , whichever is lower and calculate r 1 using the fol- lowing equation: 8) place the third pole (f p3 ) at 1/2 the switching fre- quency and calculate c cf from: 9) calculate r 2 as: where v fb = 0.6v. rr v vv fb out fb 21 = ? c fr cf sw f = 1 205 . r fc r zi i 1 2 1 2 = ? r fc i pi = 1 2 2 : gain gain so mod e a = 1 4 1 1 2 21 2 () = fcl fcr solving fo co out co i f r rc c flc i i co out : = () 2 4 r r f gain flc mod co out = 4 1 2 2 ()
max15002 dual-output buck controller with tracking/sequencing 24 maxim integrated typical operating circuits max15002 1.8v in c in pgnd sgnd ep in dreg2 bst2 dh2 lx2 csn2 dl2 csp2 en/track2 fb2 comp2 ilim2 pgnd2 pgood2 sel phase sync rt reg sgnd ct reset dreg1 bst1 dh1 lx1 csn1 dl1 3.3v csp1 pgnd1 en1 fb1 comp1 ilim1 pgood1 22.1k ? 46.4k ? 680pf 270 f 47 f 1 h 2.2 ? 100nf 44.2k ? 1.58k ? 71.5k ? 10k ? 2.7nf 100pf 11.0k ? 30.1k ? (1/2)cmfsh-31 (1/2) cmfsh-31 fdms8690 fdms8660 fdms8660 fdms8660 100nf 100nf 2.2 ? 11.0k ? 30.1k ? 100nf 47 f 1.4 h 2.7nf 100pf 49.1k ? 200k ? 10k ? 1.91k ? 44.2k ? 47.6k ? 560pf 150 f 100k ? 499k ? 2.3 f 100nf figure 8. coincident dual tracker with lossless current sense
max15002 dual-output buck controller with tracking/sequencing 25 maxim integrated typical operating circuits (continued) max15002 vout2 in c in pgnd sgnd ep in dreg2 bst2 dh2 lx2 csn2 dl2 csp2 en/track2 fb2 comp2 ilim2 pgnd2 pgood2 sel phase sync rt reg sgnd ct reset dreg1 bst1 dh1 lx1 csn1 dl1 vout1 csp1 pgnd1 en1 fb1 comp1 ilim1 pgood1 figure 9. dual sequencer with lossless current sense
max15002 dual-output buck controller with tracking/sequencing 26 maxim integrated typical operating circuits (continued) max15002 vout2 in c in pgnd agnd ep in dreg2 bst2 dh2 lx2 csn2 dl2 csp2 en/track2 fb2 comp2 ilim2 pgnd2 pgood2 sel phase sync rt reg sgnd ct reset dreg1 bst1 dh1 lx1 csn1 dl1 vout1 csp1 pgnd1 en1 fb1 comp1 ilim1 pgood1 figure 10. ratiometric dual tracker with accurate valley-mode current sense
max15002 dual-output buck controller with tracking/sequencing 27 maxim integrated pwm controller applications information power dissipation the 40-pin tqfn thermally enhanced package can dis- sipate up to 2.96w. calculate power dissipation in the max15002 as a product of the input voltage and the total reg output current (i reg ). i reg includes quies- cent current (i q ) and the total gate drive current (i dreg_ ): p d = v in x i reg i reg = i q + [f sw x (q g1 + q g2 + q g3 + q g4 )] where q g1 to q g4 are the total gate charge of the low- side and high-side external mosfets. f sw is the switching frequency of the converter and i q is the qui- escent current of the device at the switching frequency. use the following equation to calculate the maximum power dissipation (p dmax ) in the chip at a given ambi- ent temperature (t a ): p dmax = 37 x (150 - t a ).mw pcb layout guidelines use the following guidelines to layout the switching voltage regulator. 1) place the in, reg, and dreg_ bypass capacitors close to the max15002. 2) minimize the area and length of the high-current loops from the input capacitor, upper switching mosfet, inductor, and output capacitor back to the input capacitor negative terminal. 3) keep the current loop formed by the lower switch- ing mosfet, inductor and output capacitor short. 4) keep sgnd and pgnd isolated and connect them at one single point close to the negative terminal of the input filter capacitor. 5) run the current-sense lines csp_ and csn_ close to each other to minimize the loop area. 6) avoid long traces between the reg/dreg_ bypass capacitors, driver output of the max15002, mos- fet gates, and pgnd. minimize the loop formed by the dreg_ bypass capacitors, bootstrap diode, bootstrap capacitor, high-side driver output of the max15002, and upper mosfet gates. 7) place the bank of output capacitors close to the load. 8) distribute the power components evenly across the board for proper heat dissipation. 9) provide enough copper area at and around the switching mosfets, and inductor to aid in thermal dissipation. 10) connect the max15002 exposed pad to a large copper plane to maximize its power dissipation capability. connect the exposed pad to sgnd. do not connect the exposed pad to the sgnd pin (pin 35) directly underneath the ic. 11) use 2oz copper to keep the trace inductance and resistance to a minimum. thin copper pcbs com- promise efficiency because high currents are involved in the application. also, thicker copper conducts heat more effectively, thereby reducing thermal impedance.
max15002 dual-output buck controller with tracking/sequencing 28 maxim integrated chip information process: bicmos max15002 tqfn top view 35 36 34 33 12 11 13 sel dl1 dreg1 lx1 dh1 14 reg fb2 comp2 ilim2 pgood2 n.c. n.c. csp2 csn2 12 ep sync 456 + 7 27 28 29 30 26 24 23 22 sgnd rt dreg2 dl2 pgnd2 pgood1 pgnd1 en/track2 3 25 37 phase fb1 38 39 40 reset ct in en1 comp1 ilim1 n.c. 32 15 lx2 n.c. 31 16 17 18 19 20 dh2 bst1 csn1 csp1 bst2 8910 21 n.c. pin configuration package type package code outline no. land pattern no. 40 tqfn-ep t4066-3 21-0141 90-0054 package information for the latest package outline information and land patterns (foot- prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status.
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 ________________________________ 29 ? 2012 maxim integrated products, inc. the maxim logo and maxim integrated are trademarks of maxim integrated products, inc. max15002 dual-output buck controller with tracking/sequencing revision history revision number revision date description pages changed 0 12/07 initial release 1 6/08 corrected figure 8 24 2 10/12 updated mosfet gate drivers section 13

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